1. Field of the Invention
The present invention relates to a semiconductor device and a test method thereof, and more particularly relates to a semiconductor device that includes a plurality of core chips and an interface chip for controlling the core chips and a test method thereof.
2. Description of the Related Art
A memory capacity that is required in a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) are increasing every year. Increasing a memory capacity of a memory chip may use finer processing being performed on the memory chip. Therefore, in recent years, a memory device that is called a multi-chip package where plural memory chips are laminated is suggested to satisfy the required memory capacity (see Japanese Patent Application Laid-Open (JP-A) No. 2002-305283). However, since the memory chip used in the multi-chip package is a common memory chip capable of operating even though the memory chip is a single chip, a so-called front end unit that performs a function of an interface with an external device is included in each memory chip. For this reason, it is difficult to greatly increase a memory capacity for each chip.
In addition, a circuit that constitutes the front end unit is manufactured at the same time as a back end unit including a memory core, regardless of the circuit being a circuit of a logic system. It may be difficult to speed up the front end unit.
As a method to resolve the above problem, a method that detaches the front end unit from each memory chips and integrate them in one interface chip and laminates these chips, thereby constituting one semiconductor memory device, is suggested (see JP-A No. 2007-157266 or JP-A No. 2006-313607). According to this method, with respect to memory chips (Hereafter, a memory chip whose front end unit was detached is called ‘a core chip’.), it becomes possible to increase a memory capacity for each chip because an occupied area assignable for the memory core increases. Meanwhile, with respect to an interface chip that is integrated with the front end unit, it becomes possible to form its circuit with a high-speed transistor because the interface chip can be manufactured using a process different from that of the memory core. In addition, since the plural core chips can be allocated to one interface chip, it becomes possible to provide a semiconductor memory device that has a large memory capacity and a high operation speed as a whole.
As a test method of a semiconductor device, a “parallel test” has been known, in which a plurality of bit data (bit data to be stored in more memory cells than memory cells simultaneously activated at the time of normal operation) are output at the same time, and a result of comparing their outputs is output to outside as a test result (see Japanese Patent Application Laid-open No. H11-339499). A test time can be shortened by performing the parallel test.
However, in the above conventional multichip package or a semiconductor device including a plurality of core chips and an interface chip, there has been a problem that it takes a long time to perform a test. This problem is explained in detail below with the latter case as an example.
In the semiconductor device including a plurality of core chips and an interface chip, a data terminal of each of the core chips is connected to an external data terminal provided on the interface chip via a through silicon via that is commonly connected to the core chips and the interface chip. Because the test result is also output as a type of data, it is output to outside via the through silicon via. Therefore, the test results cannot be output from the core chips in a simultaneous manner, requiring them to be output in a sequential manner, thus taking a long time to perform the test.
Therefore, it has been desired to shorten the time required for a test of the above conventional multichip package or the semiconductor device including a plurality of core chips and an interface chip.